Digital clocks

ABSTRACT

A digital clock comprises a plurality of luminous digit display tubes which are arranged to display times, a source of clock pulse of a predetermined frequency, and electronic counter means responsive to the clock pulse for operating the digit display tubes in a predetermined sequence.

United States Patent 1191 1111 3,910,030 Iwade Oct. 7, 1975 [54] DIGITALCLOCKS 3,760,584 9/1973 Dargetti 58/38 3,762,152 10/1973 Marz 58/85.5[751 lnvemor- Japan 3,777,471 12/1973 Koehler et al. 58/85.5 R 73Assigneez 1 Electronics Corporation, lse 3,823,545 7/1974 V 1tt0Z58/85.5 X Japan 3,823,551 7/1974 Rlehl 58/50 R [22] Filed: Sept. 12,1973 Primary Examiner-Edith Simmons Jackmon [21] AppL NQZ 397,123Attorney, Agent, or Firm-Roland Plottel, Esq.

[52] US. Cl 58/50 R; 58/34; 58/85.5 [57] BSTRACT 51 Int 2 04 19 30; 04 900; 0043 9/00 A digital clock comprlses a plurality Of luminous digit 58Field Of Search 58/50 R, 34, 85.5; display tubes which are arranged to py times, a 340/336 source of clock pulse of a predetermined frequency,and electronic counter means responsive to the clock 5 References Citedpulse for operating the digit display tubes in a prede- UNITED STATESPATENTS Sequence- 3,626,687 12/1971 Fondiller et al. 58/24 7 Claims, 20Drawing Figures US. Patent Oct. 7,1975 Sheet4 of7 3,910,030

2 E 1" mums unsnvzu wa-wv M 01 Pill 01 M1 mm mm mm mm [mm mm mm vunFLIP-FLUP U.S. Patent Oct. 7,1975 Sheet 7 of7 3,910,030

Fig.6A Fig.6B

Fig.fi6. I Fig.

F/G./3 F/G./4

0 HHHHHHLL F 1 LHHLLLLL 2 HHLHHLHL A+A-B=X 3HHHHLLHL ALHHLLHHH 5HLHHLHHLa HLHHHHHL YHHHLLLLL HHHHHHHL HHHHLHHL DIGITAL CLOCKS BACKGROUND OF THEINVENTION This invention relates to a digital clock, more particularly adigital clock driven by an electronic driving circuit.

A digital clock of early stage comprises a plurality digit wheels whichare arranged side by side so as to display the time, in terms ofminutes, hours and or days and are driven by mechanical means such as anelectric motor and gear trains. Accordingly, the adjustment of thedisplayed time can be accomplished relatively simply in a manner similarto ordinary clocks. However, modern digital clocks utilize luminescentdisplay tubes, each having a plurality of luminous segments which arearranged in a predetermined pattern, for example a letter 8. Acomplicated electronic driving circuit is used to selectively energizedthe luminous segments so as to selectively display one of 10 digitsthrough 9. Accordingly, it is impossible to readily change the displayeddigits as in the mechanical clocks.

SUMMARY OF THE INVENTION Accordingly an object of this invention is toprovide a novel electronic digital clock which has compact constructionand is easy to operate.

It is an object of this invention to provide an improved electronicdigital clock capable of adjusting at a high speed the displayed digits.

According to this invention there is provided a plurality of luminousdigit display tubes which are arranged to display times, a source ofclock pulse of a predetermined frequency, and electronic counter meansresponsie to said clock pulse for operating said digit display tubes ina predetermined sequence.

BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings,

FIG. I shows a perspective view of a digital clock to which theinvention can be applied;

FIG. 2 shows an arrangement of the luminous segments of a display tubefor displaying letters A and P in the PM AM display section;

FIGS. 3A and 3B show letters A and P, respectively, displayed by thedisplay tube shown in FIG. 2;

FIG. 4 shows an arrangement of the luminous segments of a digit displaytube utilized in the time display section of the digital clock shown inFIG. 1;

FIG. shows digits 0 to 9 inclusive displayed by the digit display tubeshown in FIG. 4;

FIG. 6 shows connections between FIGS. 6A, 6B, 6C and 6D brieflyexplained hereunder;

FIGS. 6A, 6B, 6C and 6D, when combined in accordance with indications,show a block diagram of one embodiment of a digital clock embodying theinvention;

FIGS. 7 to 11 show diagrams to explain the operations of the firsttofourth binary counters and of the control flip-flop circuit shown inFIGS. 6C and 6D;

FIGS. 12 and 13 show the relationship between the input signals and theoutput signals of the decoding circuits to 18 shown in FIG. 6B;

FIG. 14 shows a connection diagram of the exclusive gate circuitsutilized in FIGS. 6A and 6C;

FIG. 15 shows a connection diagram of the coincidence gate circuitutilized in FIG. 6A.

DESCRIPTION OF THE PREFERRED EMBODIMENT A digital clock shown in FIG. 1comprises an AM PM display section 1 including two display tubes la andlb for displaying forenoon (AM) and afternoon (PM) and a time displaysection 2 including four digit display tubes 2a, 2b, 2c and 2d fordisplaying minutes, tens minutes hours and tens hours, respectively.

As shown in FIG. 2, the display tube la of the AM PM display section '1comprises 6 luminous segments 3a through 3f. When all of these segmentsare energized a letter A meaning AM is displayed as shown in FIG. 3Awhereas when segments 3a through 3c are energized a letter P meaning PMis displayed. In other words, letters A and P are selectively displayeddependent upon whether segment 3f is energized or not.

Each of the digit display tubes 2a to 2d of the time display section 2comprises 8 luminous segments 4a through 4h which are arranged as shownin FIG.-4 and by the selective energization of these luminous segmentsit is possible to display any one of digits 0 through 9 as shown in FIG.5.

As shown in FIGS. 6A, 6B, 6C and 6D, the digital clock of this inventioncomprises an input terminal 5 which is connected to receive a clockpulse of 1 MHz from a crystal oscillator, not shown, and a frequencydivider 6 which is connected to receive the 1 MHz clock pulse fordelivering a 1 Hz pulse to output terminal 6a and a l/ Hz pulse tooutput terminal 6b. To display the time, there are provided a first 4bit binary counter 7 which operates as shown in FIG. 7 for displayingminutes, a second 3 bit binary counter 8 which operates as shown in FIG.8 for displaying tens minutes, a third 4 bit binary counter 9 whichoperates as shown in FIG. 9 for displaying hours a fourth 2 bit binarycounter 10 which operates as shown in FIG. 10 for displaying tens hoursand a control flip-flop circuit 11 which operates to control theluminous segment 3f of the display tube 1a of the AM PM display section1 in a manner shown in FIG. 11. There are also provided AND gatecircuits 12a through 12z, NOT gate circuits 13a through 13d, OR gatecircuits 14a through 14s, first to fourth decoders 15 through 18 forminutes, tens minutes, hours and tens hours which are connected to firstto fourth segment drivers 19 through 22 respectively for minutes, tensminutes, hours and tens hours.

The outputs of segment drivers 19 through 22 are connected to respectiveluminous segments of digit display tubes 2a to 2d respectively. Thereare provided exelusive gate circuits 23a through 23n, each having aconstruction as shown in FIG. 14, manual time selectors 24a through 24dfor setting minutes, tens minutes, hours" and tens hours respectively, aAM PM transfer switch 25 for controlling the energization of theluminous segment 3f of the diaplay tube 1a, time setting decoders 26athrough 26d for minutes, tens minutes, hours and tens hours,respectively, a coincidence gate circuit 27 having a construction asshwon in FIG. 15, a' flip-flop circuit 28, a chime 29, and a flip-flopcircuit 30 for controlling luminous segment 3f of the display tube la ofthe AM PM display section l. I v

31 designates a first selector switch provided with a stationary contact31a for use in clocks for displaying l2 oclocks and a stationary contact31b for use in clocks for displaying 24 oclocks, 32 designates a secondselector switch provided with a stationary contact 32a for setting thenoon at 12 oclock, and a stationary contact for setting the noon at Oocloc'k,'and 33 designates a display selector switch provided'with astation ary contact 33b for displaying on the AM PM display section 1and the time display section 2 the time set by the manual time setters24a through 24d for minutes, tens minutes, hours and tens hoursrespectively, and by the AM PM transfer switch 35,.and an idlestationary contact 33a which does not display any time. 34 designates amanual switch which is used to open AND gate circuit 12a for supplyingthe clock pulse directly to the first binary counter 7 when it isoperated to manually set the time.

In operation, the 1 MHz clock pulse supplied to input terminal 5 entersinto frequency divider 6 which supplies a pulse of 1/60 Hz tothe firstbinary counter 7-via output terminal 6h and OR gate circuit 14a. Inresponse to this pulse, the binary counter 7 operates in a manner asshown in FIG.v 7 and when its content reaches LHLH, AND gate circuit 12bis opened to reset the first binary counter 7 and to supply the contentof the first binary counter 7 to the second binary counter 8. The secondbinary counter 8 continues its operation until its content reaches LHHat which time AND gate circuit 120 is opened to reset the second binarycounter 8 and to supply the content thereof to the third binary counter9. Accordingly, th'e'third binary counter 9 operates in a manner asshown in FIG. 9 and when its content reaches LHLH AND gate circuit 1211is opened to reset the third binary-counter 9 and to supply the contentthereof to the fourth binary counter 10.

A. l2 0 clock clock wherein the noon is displayed as oclock The firstselector switch 31 is thrown to the stationary contact 31a forestablishing a L level and the second selector switch 32 is thrown tothe stationary contact 32b for establishing a H level. After displayingthe times AMl, AM2, AM3 the third binary counter 9 operates. AND gatecircuit 12d is opened when the content of the third binary counter 9reaches LHLL which shows 2, -when the content of the fourth binarycounter '10 reaches HL which shows .1 and when the control flip-flopcircuit 11 assumes H level which shows AM, whereby the third binarycounter 9 is reset via OR gate circuit 14r, the fourth binary counter 10is reset through OR gate 14s, and the control flip-flop circuit 11 isset to the L level state which shows the PM. In this manner, afterdisplaying the noon as PMO and thence the times PMl, PM2 when thecontrol flip-flop circuit 11 is set to level L which shows PM, AND gatecircuit 12a opens whenthe content of the third binary counter 9 reachesLHLL which shows 2 and when the content of the fourth binary counter 10reaches HL which shows 1. Opening of the AND, gate circuit 120 displaysthe times AM1 ,-AM2 in the same manner as above described. In thismanner, the clock can operate as a 12 oclock wherein the noon isdisplayed as 0 oclock.

B. 24 oclocks clock wherein the noon is displayed as l2 oclocks lish Llevel. After displaying the times AMI, AM2 the third binary counter 9operates. When its content reaches HHLL which represents 3, AND gatecircuit 12g is opened when the content of the fourth binary counter 10reachesI-IL which represents 1. Consequently the third and fourth binarycounters 9 and 10 continue to count without being reset and the controlflip-flop circuit 11 is set to L level which represents PM.Consequently,.the display in the AM -.PM display section is changed fromAM to PM so that thereafter times PM13,,PM14;, are sequentiallydisplayed.

Then when the third binary counter 9 operates to ar range its content toHLHL which represents 5, AND

gate circuit, 12f is opened when the content of the fourth counter 10reaches LH which represents 2 whereby the third binary counter 9 isreset via OR gate circuits 14q and Mr, the fourth binary counter l0'isreset via OR gate circuit 14s and the control flip-flop circuit 11 isset to L level'representing AM. Accordingly, the display in the AM PMsection is changed to AM, and thereafter times AMI, AM2 are sequentiallydisplayed. In this manner, the clock operates as 24 oclocks clockwherein the noon is displayed as 12 C. 12 oclocks clock wherein the noonis displayed as 12 oclocks The first selector switch 31 is thrown tostationary contact 310 for establishing L level. After displaying thetimes AMl, AM2 the third binary counter 9 operates. When the contentthereof reaches HHLL which represents 3, when the content of the fourthbinary counter 10 reaches HL which represents 1 and when the controlflip-flop circuit 11 assumes H level which represents AM, AND gatecircuit 12g is opened whereby the fourth binary counter 10 is resetviaOR gate circuit 14s and the control flip-flop circuit 11 is set tolevel L which represents PM. Consequently, the display in the AM PMdisplay section 1 is changed to PM displaying aftemoonJThereafter',times PMl, PM2 are displayed sequentially. When the content of the thirdbinary counter 9 reaches LHLL which represents 2 and when the contentofthe fourth binary counter 10- reaches' HL which represents 1, AND gatecircuit 12c is opened whereby the display in the AM PM display sectionis changed to'AM representing forenoon and thereafter times AMI, AM2 aredisplayed sequentially. In this manner, the clock can operates as a 12oclocks clock wherein the noon is displayed as 12 0'- clocks. i

As above described first to fourth binary counters 7 through 10 andcontrol flip-flop circuit 11 operate in a mannervas shown in FIGS. 7through 11, and the outputs of these circuit elements are applied todecoders 15 through 18 via OR gate circuitsl4b through 14p and AND gatecircuits l2i through 1 2w. The decoders 15 through 18 operate as showninFIG. 13 so that their outputs 'luminesce respective luminous segmentsof digit display tubes 2a through 2d of the time display section 2 viasegment drivers 19 through 22, respectively thereby selective bydisplaying the digits 0 to 9 shown in FIG. 5.

AND gate circuit 121' through 12w operates as follows. When the displayselector switch 33 is thrown to stationary contact 33a to establish Llevel, the two inputs to each one of exclusive gate circuits 23a through23n assume L level to provide an output of H level.

These H level outputs are supplied to one inputs of respective AND gatecircuits l2i through 12wso that these AND gate circuits are opened bythe pulses applied to the other inputs thereof. 0

When AM and PM are displayed for displaying forenoon and afternoon, asthe display tubes la and 1b of the AM PM section 1 are driven by a 1 Hzpulse having a period of one second which'is supplied through outputterminal 6a of the frequency divider 6 these display tubes are caused toflicker at a frequency of one per second.

The luminous segment 3f of the display tube 1a of the AM PM section 1 isenergized when the output terminal Q of the controlled flip-flop circuit11 assumes H level, which is applied to luminous segment 1b via OR gatecircuit 14p, AND gate circuits 12w and 12y and flip-flop circuit 30.

When the output terminal Q of the control flip-flop circuit 11 assumes Hlevel or when its output terminal Q assumes L level, OR gate circuit 14pand AND gate circuit 12w produce outputs of L level which are convertedinto a signal of H level by the operation of NOT gate circuit 13d toreset flip-flop circuit 30 via AND gate circuit 12x thus deenergizingthe luminous segment 3f.

In this manner AM and PM respectively representing forenoon andafternoon are alternatively displayed and the displays AM and PM arecaused to flicker once per second.

Time adjustments are performed in the following manner.

The AM PM transfer switch25 is operated to select forenoon AM orafternoon PM. Then, manual time selectors 24a through 24d are operatedto set any desired time. The outputs of the manual time selectors 24athrough 24d are decoded by the time setting decoders 26a through 26d asshown in FIGS. 7 through and the outputs of these decoders are appliedto exclusive gate circuits 23a through 23n.

When manual switch 34 is thrown to stationary contact 34a, the frequencydivider 6 will be reset by the clock pulse and the clock pulse will beimpressed upon first to fourth digital counters 7 through 10 via ANDgate circuit 12a thereby operating these counters at a high speed.

On the other hand, when the display selector switch 33 is thrown to thestationary contact 33b to establish H level which is applied to oneinputs of respective exclusive gate circuits 23a through 23n. Further,as the signal representing AM or PM selected by the AM PM transferswitch 25 and the signals representing the times which have been set bythe manual time setters 24a through 24d are applied to the other inputsof the exclusive gate circuits 23a through 23n they produce Outputs of Hlevel which are applied to one inputs of AND gate circuits 121' through12w. Consequently, the outputs from the first to fourth binary counters7 through 10 and from the control flip-flop circuit 11 are applied tothe display tubes of the AM PM display section 1 and the time displaysection 2 thereby displaying AM or PM together with time. The outputsfrom binary counters 7 through 10 and from the control flip-flop circuitare also applied to the coincidence circuit 27 whereby the coincidenceof the outputs from the AM PM transfer switch 25, time setters 24athrough 24d. control flip-flop circuit 11 and first to fourth binarycounters 7 through 10 is determined. The coincidence output from thecoincidence circuit 27 is sent to chime 29 via flip-flop circuit 28thereby operating the chime. The coincidence output is also sent to ANDgate circuit 12a via NOT gate circuit thereby closing AND gate circuit12a. Closure of the AND gate circuit 12a terminates the high speed timeadjusting operation provided by the first to fourth binary counters 7through 10 and the control flip-flop circuit 11. Immediately thereafter,manual switch 34 is thrown to stationary contact 34b thereby restoringthe normal operation of the frequency divider 6 to close AND gatecircuit 12a. Thereafter, the normal time display operation is performed.

Although, in the foregoing description, first to fourth binary counterswere assumed to have different number of bits it will be clear that theycan have the same number of bits.

Furthermore, it will be clear that the AM PM display section may becaused to flicker at any desired frequency other than once per second.

As above described, the invention provides a novel digital clock inwhich the time displayed by digit display means can be adjusted at ahigh speed.

Although the invention has been shown and described in terms of itspreferred embodiment it will be clear that the invention is by no meanslimited thereto but many changes and modifications will be obvious toone skilled in the art without departing from the true spirit and scopeof the invention.

What is claimed is:

1. A digital clock comprising a plurality of digit display meansarranged to display times,

a source of clock pulses,

first means responsive to said clock pulses for producing a first outputto operate said digit display means in a predetermined sequence, manualmeans including means for entering desired times to be displayed coupledto said first means to produce a second output from said first means tooperate said first means in the same sequence but at a high speed forrapidly changing the time displayed by said digit display means, and

coincidence means for comparing said times displayed by said digitdisplay means and said desired times in said means for entering and fordiscontinuing said second output from said first means on coincidence.

2. A digital clock comprising a plurality of digit display meansarranged to display times, a source of clock pulse of a predeterminedfrequency, a frequency divider for converting said clock pulse into apulse of lower frequency, binary counter means for counting said pulseof lower frequency for operating said digit display means in apredetermined sequence, manually operated time setting means, meanscontrolled by said manually operated time setting means for causing saidbinary counter means to count said clock pulse, a coincidence circuitfor detecting the coincidence between the desired times in said manuallyoperated time setting means and the content of said counter means andfor controlling said controlled means to stop said binary counter meansfrom counting said clock pulse.

3. The digital clock according to claim 2 wherein means is providedincluding logic input and manual switch to cause said clock to operateeither a 24 oclocks clock or a 12 oclocks clock.

4. The digital clock according to claim 2 which further comprisesdisplay tubes for selectively displaying AM andPM. v I i 5. The digitalclock according to claim 4 which further comprises means for flickeringthe display of said AM and PM at a predetermined frequency.

6. The digital clock according to claim 2 wherein said digital displaymeans comprises four luminous display tubes for displaying minutes, tensminutes, hours and tens hours respectively, each of said luminousdisplay tubes includingalpluralityof luminous segments which areselectively energized to display any one of ten digits through 9, andwherein said binary counter means comprises four serially connectedbinary counters each forcontrolling each of said luminous display tubes.

7..A digital clock comprising a plurality of digit display means adaptedto display a time, a source of clock pulse of a predetermined highfrequency, means for generating low frequency. 'pulses from said source,counter means responsive to said low frequency pulse for producing inpredetermined sequence outputs which in turn operate said plurality ofdigital display means, a plurality of manually operated time settingmeans for setting a desired time, manually operated switch means forcausing said counter means to operate at ahigh speed by said clockpulse, and a coincidence circuit for detecting the coincidence betweenthe outputs of said manually operated time setting means and saidcounter means and for disabling saidi'nanually operated switch means bythe output of said coincidence circuit, whereby the time to displayed onsaidplural-

1. A digital clock comprising a plurality of digit display meansarranged to display times, a source of clock pulses, first meansresponsive to said clock pulses for producing a first output to operatesaid digit display means in a predetermined sequence, manual meansincluding means for entering desired times to be displayed coupled tosaid first means to produce a second output from said first means tooperate said first means in the same sequence but at a high speed forrapidly changing the time displayed by said digit display means, andcoincidence means for comparing said times displayed by said digitdisplay means and said desired times in said means for entering and fordiscontinuing said second output from said first means on coincidence.2. A digital clock comprising a plurality of digit display meansarranged to display times, a source of clock pulse of a predeterminedfrequency, a frequency divider for converting said clock pulse into apulse of lower frequency, binary counter means for counting said pulseof lower frequency for operating said digit display means in apredetermined sequence, manually operated time setting means, meanscontrolled by said manually operated time setting means for causing saidbinary counter means to count said clock pulse, a coincidence circuitfor detecting the coincidence between the desired times in said manuallyoperated time setting means and the content of said counter means andfor controlling said controlled means to stop said binary counter meansfrom counting said clock pulse.
 3. The digital clock according to claim2 wherein means is provided including logic input and manual switch tocause said clock to operate either a 24 o''clocks clock or a 12o''clocks clock.
 4. The digital clock according to claim 2 which furthercomprises display tubes for selectively displaying AM and PM.
 5. Thedigital clock according to claim 4 which further comprises means forflickering the display of said AM and PM at a predetermined frequency.6. The digital clock according to claim 2 wherein said digital displaymeans comprises four luminous display tubes for displaying minutes, tensminutes, hours and tens hours respectively, each of said luminousdisplay tubes including a plurality of luminous segments which areselectively energized to display any one of ten digits 0 through 9, andwherein said binary counter means comprises four serially connectedbinary counters each for controlling each of said luminous displaytubes.
 7. A digital clock comprising a plurality of digit display meansadapted to display a time, a source of clock pulse of a predeterminedhigh frequency, means for generating low frequency pulses from saidsource, counter means responsive to said low frequency pulse forproducing in predetermined sequence outputs which in turn operate saidplurality of digital display means, a plurality of manually operatedtime setting means for setting a desired time, manually operated switchmeans for causing said counter means to operate at a high speed by saidclock pulse, and a coincidence circuit for detecting the coincidencebetween the outputs of said manually operated time setting means andsaid counter means and for disabling said manually operated switch meansby the output of said coincidence circuit, whereby the time to bedisplayed on said plurality of digit display means is rapidly adjusted.